(a) Fields of the Invention
The present invention relates to semiconductor devices used as, for example, DRAMs (Dynamic Random Access Memories), and to their fabrication methods.
(b) Description of Related Art
In recent years, as DRAMs as semiconductor memory devices have been increasing in capacity, miniaturization thereof has been advancing. Capacitor structures of the DRAMs are roughly classified into: a trench structure in which a trench is formed in a silicon substrate and a capacitor is formed inside the formed trench; and a stacked structure in which a capacitor is formed in a stacked film over a substrate. In order to accomplish miniaturization of the DRAM, a trench-shaped stacked capacitor structure is employed as the stacked capacitor. This structure is constructed so that a trench for forming a capacitor is formed in an interlayer insulating film, and a lower electrode, a capacitor insulating film, and an upper electrode are sequentially provided on a side wall and a bottom surface of the trench. For such a trench-shaped stacked capacitor structure, in order to maintain the charge retention capability and ensure a sufficient cell capacitance, the trench for forming the capacitor should be formed to have a greater depth. Along with this formation, a contact plug for connecting an interconnect layer to the substrate should also be elongated. Therefore, the following requirements are demanded of the trench-shaped stacked capacitor structure: suppression of parasitic capacitance, which is produced between the upper electrode and the interconnect, by providing the sufficiently-thick interlayer insulating film on the upper electrode; and easy formation of the contact plug penetrating the interlayer insulating film.
Herein, description will be made of a conventional DRAM with a typical trench-shaped stacked capacitor as shown in, for example, Japanese Unexamined Patent Publication No. 2004-349462 and its fabrication method. FIG. 4 is a sectional view showing the structure of the conventional DRAM with the stacked capacitor.
Referring to FIG. 4, the conventional DRAM includes: a silicon substrate 501; a DRAM cell transistor gate 502 formed over the silicon substrate 501; a first interlayer film 503 formed on the silicon substrate 501 and the DRAM cell transistor gate 502; first contact plugs 504a and 504b which are formed on impurity diffusion layers (not shown) provided in the silicon substrate 501, respectively, and which penetrate the first interlayer film 503; a silicon nitride film 505 formed on the first interlayer film 503; and a second interlayer film 506 formed on the silicon nitride film 505 and provided with a trench reaching the top surface of the first contact plug 504a. 
Furthermore, the conventional DRAM is formed with: a lower electrode 509, a capacitor insulating film 510, and an upper electrode 513 sequentially formed from bottom to top in the trench provided in the second interlayer film 506; a third interlayer film 515 formed on the upper electrode 513 and the second interlayer film 506; and a second contact plug 516 formed on the first contact plug 504b and penetrating the second interlayer film 506 and the third interlayer film 515. Through the first contact plug 504a, the impurity diffusion layer and the lower electrode 509 are electrically connected to each other.
As described above, the conventional DRAM shown in FIG. 4 has the structure in which a portion of the upper electrode 513 is formed above the second interlayer film 506 and the top surface of the upper electrode 513 and the side surface of the top end thereof are in contact with the third interlayer film 515.
Next, a conventional method for fabricating a DRAM with a stacked capacitor will be described with reference to the accompanying drawings. FIGS. 5A to 5I and 6A to 6C are sectional views showing the conventional method for fabricating a DRAM, respectively.
Referring to FIG. 5A, first, the DRAM cell transistor gate 502 is formed above the silicon substrate 501, and then the first interlayer film 503 is formed on the silicon substrate 501 and the DRAM cell transistor gate 502. Then, the first contact plugs 504a and 504b penetrating the first interlayer film 503 are formed on the impurity diffusion layers (not shown) formed in the silicon substrate 501, respectively.
Next, as shown in FIG. 5B, the silicon nitride film 505 is deposited on the first interlayer film 503 and the first contact plugs 504a and 504b. Thereafter, as shown in FIG. 5C, on the silicon nitride film 505, the second interlayer film 506 is formed by a chemical vapor deposition (CVD) method.
Subsequently, as shown in FIG. 5D, through the second interlayer film 506, a trench 507 reaching the top surface of the first contact plug 504a is formed by a lithography method and a dry etching. Thereafter, as shown in FIG. 5E, a first conductive film 508 is deposited on the inner surface of the trench 507 and the top surface of the second interlayer film 506. Then, as shown in FIG. 5F, by a lithography method and a dry etching, the first conductive film 508 deposited on the top surface of the second interlayer film 506 is removed so that it remains only on the inner surface of the trench 507, thereby forming the lower electrode 509 made of the first conductive film.
As shown in FIG. 5G, the capacitor insulating film 510 is deposited on the second interlayer film 506 and the lower electrode 509, and then a second conductive film 511 is deposited on the capacitor insulating film 510.
Next, as shown in FIG. 5H, on the second conductive film 511, a photoresist mask 512 is formed by a lithography method. Thereafter, as shown in FIG. 5I, portions of the capacitor insulating film 510 and the second conductive film 511 are removed by a dry etching using the photoresist mask 512 as a mask to form a capacitor having the lower electrode 509, the capacitor insulating film 510, and the upper electrode made of the second conductive film 511. In the manner described above, the portion of the upper electrode 513 is formed above the second interlayer film 506.
Subsequently, as shown in FIG. 6A, for example, a silicon oxide film 514 is deposited on the second interlayer film 506 and the upper electrode 513. In this deposition, the silicon oxide film 514 is made thicker than the upper electrode 513.
As shown in FIG. 6B, the silicon oxide film 514 is planarized by polishing through a chemical mechanical polishing (CMP) method, thereby forming the third interlayer film 515. Thereafter, as shown in FIG. 6C, the second contact plug 516 penetrating the second interlayer film 506 and the third interlayer film 515 is formed on the first contact plug 504b. 
In the conventional DRAM fabrication method described above, in forming the third interlayer film 515, the insulating film having a greater thickness than the upper electrode 513 is deposited. Thereby, a step resulting from the height difference between the upper electrode 513 and the second interlayer film 506 is made gentle, and then planarization is performed by the CMP method or the like.